1. Field of the Invention
The present invention relates to a display device having thin film transistors serving as switching elements formed on a transparent insulating substrate and to a driving method of the same and electronic equipment incorporating the same, and particularly to an improvement of a signal line driving technique.
2. Description of the Related Art
Display devices such as liquid crystal display devices (liquid crystal displays) using liquid crystal cells as pixel display elements (electro-optical elements) are active matrix image displays. Display devices of this type are designed to display an output image via a liquid crystal display surface.
Thanks to their slimness and low power consumption, liquid crystal display devices have found application in a variety of electronic equipment including mobile information terminals (personal digital assistant: PDA), mobile phones, digital cameras, video cameras, and computer display devices.
Incidentally, screen flickering is typically not perceivable by human eyes if the image frame rate is 60 Hz or higher.
At this frequency, however, blurriness in moving images as well as still images is perceivable by humans.
To provide an improvement to this problem, namely, eliminating blurriness in a moving image, a frame frequency of 240 Hz, four times higher than 60 Hz, is desired as disclosed, for example, in Japanese Patent Laid-Open No. 2006-78505 (hereinafter referred to as Patent Document 1).
As for the writing scheme using thin film transistors (TFTs), the display method disclosed in Patent Document 1 writes a frame image in 1/240 of a second with pixels sequentially displayed from left. Alternatively, the display method performs a refresh in seemingly 1/240 of a second by shifting the time and writing to liquid crystals in 1/60 of a second (FIG. 21 in Patent Document 1).
On the other hand, a technique is disclosed in Japanese Patent Laid-Open No. Hei 11-338438 (hereinafter referred to as Patent Document 2) which allows for writing of video data at a data transfer rate of around MHz.
This liquid crystal display device stores a line of data in a memory circuit 2 via switch 1, as illustrated in FIG. 1. Then, during a next line interval, the same device selects red (R) video data from among red (R), green (G), and blue (B) video data while at the same time storing the video data in a memory circuit 3 using switches 4-1 to 4-3.
Then, the same device reads the R data for a single driver IC from the memory circuit via a switch 5-1 (or 5-2 or 5-3). The switches 5-1 to 5-3 are switched together with a switch 1. The same device writes the data to a driver IC 6-1 (or 6-2 or 6-3) and at the same time writes the data to another driver IC. The same device writes green (G) and blue (B) video data in the same manner. This allows different pieces of video data to be written to the respective driver ICs at the same time. A liquid crystal display panel 7 displays video based on the video data written to the driver ICs.
However, no description is made in the aforementioned Patent Document 1 as to the input timings (input method) of image signal data to data line drive circuits. No specific data writing system has been established for an image frame frequency of 240 Hz.
On the other hand, the technique disclosed in Patent Document 2 writes image data to the driver ICs 6-1 to 6-3 synchronously with each other. Further, the pieces of data supplied to the three driver ICs are synchronous with each other.
This condition leads to increased noise at the leading or trailing edge of the clock and image data between adjacent wirings, giving rise to a voltage fluctuation of the image data and clock signal themselves and making the data and clock unstable.
The input of deformed image data causes an error in the driver IC image data, significantly degrading the image quality. Waveform shaping by a buffer circuit produces a waveform prone to data error.
At a frequency beyond 100 MHz in particular, noise between adjacent wirings in a cable or printed board is hardly negligible.
Today, VGA (800×600 pixels) desires a clock frequency of 27 MHz, and 108 MHz at a high frame rate which is four times higher in speed.
Further, with UVGA (1600×1400 pixels), the minimum clock frequency is 135 MHz. The frequency four times greater than 135 MHz is 540 MHz, which is uncontrollable by an ordinary printed board.
This is the reason why division driving is desired. However, the driving of four or five divisions is considered to be the limit in terms of the scale of the panel system.
In this condition, a potential develops due to high frequency components arising from the parasitic capacitance between adjacent wirings adapted to supply signals to the driver ICs. This potential manifests itself as noise in the clock and image data, causing an error in the clock signal and image data and eventually degrading the panel image quality.
A purpose of the embodiment of the present invention is to provide a display device allowing for loading of high frequency image data without degrading the image quality, a driving method of the same, and electronic equipment incorporating the same.